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74AS00 Quad 2-Input NAND Gate. Physical Dimensions inches (millimeters) unless otherwise noted (Continued). Lead Plastic Dual-In-Line Package ( PDIP). 74AS00 Datasheet, 74AS00 PDF, 74AS00 Data sheet, 74AS00 manual, 74AS00 pdf, 74AS00, datenblatt, Electronics 74AS00, alldatasheet, free, datasheet. description. These devices contain four independent 2-input positive-NAND gates. They perform the Boolean functions Y = A • B or Y = A + B in positive logic.

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Two important factors in the consideration of each logic family are speed and power consumption. Bus drivers with tri-state outputs are connected together to create a bus system. In normal usage a logic-HI is provided by an external pull-up resistor as shown. The propagation delay inherent in gates can be useful for creating oscillatory circuits. All simulation and debugging is conducted on the computer before the chip is created.

Measure both the input voltage and the logic output of the inverter. In contrast with a normal totem-pole output, it cannot be the source of current and therefore cannot present a logic-HI on its own. Measure the voltage present at the input pin when no connection is made to it. To present basic characteristic and limitations of gates. Open-Collector Output Figure 6.

How is the frequency affected by values of R and C? When G is LO, the output is in the high impedance state. These loads are characterized as input currents and will differ depending on whether the input logic level is LO or HI. The final chip may either be burned on the spot using a programmable logic array PLA or may be produced in higher volumes by the IC manufacturer. What is the smallest value of R such that the output is still LO?

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What is the difference between open collector, tri-state and totem-pole outputs? Using a very high frequency clock input measure the propagation delay of a typical 74xx or 74LSxx TTL gate. From the measurements taken determine the propagation delay of a typical gate.

Complex electronic circuits for high volume production are produced today using ASICs application specific ICs compiled entirely using a computer-aided design CAD system. Draw the input and output waveforms timing diagram.

The chart shows the datasheeet relationship of common TTL families. What is the input hysteresis in volts for these two gates? Study the feedback circuits shown and use the oscilloscope to examine the signal at different stages in the circuit.

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What is the voltage range that would be considered a logic LO? In other words, when Q3 is closed, Q4 is open. When and why would you use tri-state and datassheet outputs as opposed to totem-pole outputs?

Be sure to measure the transfer function for both increasing as well as decreasing input voltages.

This is called the high impedance or Hi-Z state. The first two conditions show the normal totem-pole operation. Observe here that the circuit elements associated with Q4 in the totem-pole circuit are missing and the collector of Q3 is left open-circuited, hence the name open-collector. What is the minimum and maximum values of R and C?

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This is useful for creating a party-line data bus or control bus whereby any one of several circuits may pull the line LO without causing damage to another active output.

What is meant by tri-state or 3-state outputs? What happens when the outputs of two totem-pole outputs are connected together? What is the minimum and maximum frequency of oscillation?

Let us examine the typical totem-pole output once datasheet. Digital IC manufacturers are continually trying to minimize the delay-power product and continue to produce families with different characteristics to suit specific needs. Calculate the range of values for this resistor.

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The voltage at the output pin is indeterminate and is said to be floating. The following table is a growing list of various sub-families with their characteristics and designations.

These two tend to be directly related, i. Why is negative logic commonly used?